---
type: claim
domain: manufacturing
description: "100% EUV market share, 83% total lithography, $350M+ per High-NA machine, ~50 systems/year production cap — ASML's 30-year co-development with Zeiss optics and TRUMPF light sources created a monopoly no competitor can replicate because the barrier is an entire ecosystem not a single technology"
confidence: proven
source: "Astra, ASML financial reports 2025, Zeiss SMT 30-year EUV retrospective, TrendForce, Tom's Hardware, Motley Fool March 2026"
created: 2026-03-24
secondary_domains: ["ai-alignment"]
depends_on:
- value in industry transitions accrues to bottleneck positions in the emerging architecture not to pioneers or to the largest incumbents
challenged_by:
- China's domestic EUV efforts have achieved laboratory-scale wavelength generation by 2024-2025 though the gap from lab to production tool is measured in years
supports:
- HBM memory supply concentration creates a three-vendor chokepoint where all production is sold out through 2026 gating every AI training system regardless of processor architecture
reweave_edges:
- HBM memory supply concentration creates a three-vendor chokepoint where all production is sold out through 2026 gating every AI training system regardless of processor architecture|supports|2026-04-04
---

# ASML EUV lithography monopoly is the deepest chokepoint in semiconductor manufacturing because 30 years of co-developed precision optics created an unreplicable ecosystem that gates all leading-edge chip production

ASML holds 100% of the EUV lithography market and 83% of all lithography. No other company on Earth manufactures EUV machines. Canon and Nikon compete only in older DUV lithography. This is not a typical market concentration — it is an absolute monopoly on the technology required for every chip at 5nm and below.

The monopoly is unreplicable because the barrier is an entire co-developed ecosystem, not a single technology or patent:

**Zeiss SMT** (Oberkochen, Germany) produces the most precise mirrors ever made. Scaled to the size of Germany, the largest surface unevenness would be 0.1mm. Each mirror has 100+ atomically precise layers, each a few nanometers thick. Making one takes months. Zeiss holds ~1,500 patents and spent 25+ years co-developing these optics with ASML. The measurement systems needed to verify subatomic-level mirror precision didn't previously exist — Zeiss and ASML had to co-invent them.

**Cymer/TRUMPF** light sources fire three lasers at 100,000 tin droplets per second to generate 13.5nm wavelength light. No conventional lens transmits EUV — it must be reflected through vacuum using the Zeiss mirrors. Each system requires components from 800+ suppliers.

**Scale:** ASML shipped 48 EUV systems in 2025, ~250 cumulative. Standard EUV (NXE series) costs $150-200M. High-NA EUV (EXE series, enabling 2nm and below) costs $350-400M. Revenue: EUR 32.7B in 2025. Market cap: ~$527B — Europe's largest tech company. Backlog: EUR 38.8B. R&D: $5.3B/year.

**ASML is the real enforcement mechanism for export controls.** China has received zero EUV machines. The Netherlands banned EUV exports in 2019 under US pressure and expanded restrictions to advanced DUV in September 2024. Controlling ASML's exports is equivalent to controlling access to leading-edge chipmaking. Chinese companies stockpiled DUV equipment aggressively (ASML sourced 49% of 2024 revenue from China), but without EUV they face severe penalties at 5nm and below.

**China's DUV workaround is viable but punitive:** SMIC achieves 5nm using quadruple-patterning DUV with ~33% yield (vs TSMC's 80%+), 50% higher cost, and 3.8x more process steps (34 steps vs 9 for EUV). This enables strategic capability (Huawei Kirin 9000s) but not commercial competitiveness. CNAS flagged this as an export control loophole in December 2025.

**ASML production capacity (~50 EUV systems/year) is a hard constraint on global fab expansion.** The number of leading-edge fabs the world can build per year is directly bottlenecked by one company's manufacturing throughput. High-NA capacity is ~5-6 units/year, targeting 20/year by 2028. Lead times are multi-year. This means ASML constrains TSMC, Samsung, and Intel's expansion plans simultaneously.

## Challenges

China has achieved EUV-range wavelength generation in laboratory conditions by 2024-2025, but has not demonstrated a production-capable integrated tool — the gap is measured in years. ASML is expanding capacity. The High-NA transition may ease some pressure by enabling more transistors per exposure. But the fundamental monopoly — rooted in 30 years of ecosystem co-development — shows no sign of eroding. Canon and Nikon have shown no public effort toward EUV. The only realistic path to a second EUV supplier would require a Zeiss-equivalent optics partner, a comparable light source, and a decade of integration — and even then it would produce a machine entering production a generation behind ASML.

---

Relevant Notes:
- [[value in industry transitions accrues to bottleneck positions in the emerging architecture not to pioneers or to the largest incumbents]] — ASML holds the deepest bottleneck position in the entire semiconductor stack
- [[CoWoS advanced packaging is the binding bottleneck on AI compute scaling because TSMC near-monopoly on interposer technology gates total accelerator output regardless of chip design capability]] — ASML gates what TSMC can fabricate; CoWoS gates what TSMC can package. Two independent bottlenecks.
- [[semiconductor fab cost escalation means each new process node is a nation-state commitment because 20B-plus capital costs and multi-year construction create irreversible geographic path dependence]] — fab cost escalation is partly driven by EUV machine costs ($150-400M per tool)
- [[TSMC manufactures 92 percent of advanced logic chips making Taiwan the single largest physical vulnerability in global technology infrastructure]] — TSMC's monopoly runs on ASML's monopoly — it's monopolies all the way down
- [[compute supply chain concentration is simultaneously the strongest AI governance lever and the largest systemic fragility because the same chokepoints that enable oversight create single points of failure]] — ASML is the ultimate chokepoint underlying all the others

Topics:
- [[manufacturing systems]]
