---
type: claim
domain: manufacturing
description: "SK Hynix, Samsung, and Micron produce all HBM globally with each GB requiring 3-4x the wafer capacity of DDR5 — structural supply tension worsens as AI chips demand more memory bandwidth per generation"
confidence: likely
source: "Astra, Theseus compute infrastructure research 2026-03-24; SK Hynix/Samsung/Micron CFO public confirmations"
created: 2026-03-24
secondary_domains: ["ai-alignment"]
depends_on:
  - "value in industry transitions accrues to bottleneck positions in the emerging architecture not to pioneers or to the largest incumbents"
challenged_by:
  - "HBM4 increases per-stack capacity which could ease the constraint if stacking efficiency improves faster than demand grows"
  - "alternative memory architectures like CXL-attached memory may reduce HBM dependency for some workloads"
---

# HBM memory supply concentration creates a three-vendor chokepoint where all production is sold out through 2026 gating every AI training system regardless of processor architecture

High Bandwidth Memory (HBM) is required for every modern AI accelerator — NVIDIA H100/H200/B200, AMD MI300X, Google TPU v5. Three companies produce all of it globally: SK Hynix (~50% market share), Samsung (~40%), and Micron (~10%). All three have confirmed their HBM supply is sold out through 2026.

The structural tension is physical: each GB of HBM requires 3-4x the silicon wafer capacity of standard DDR5 because HBM stacks multiple DRAM dies vertically using through-silicon vias (TSVs) and micro-bumps. This means HBM production directly competes with commodity DRAM production for wafer capacity, creating a zero-sum allocation problem for memory fabs.

Each new AI chip generation demands more HBM per accelerator: NVIDIA's B200 uses HBM3e stacks with higher bandwidth than H100's HBM3. The trend toward larger models and longer context windows increases memory requirements faster than stacking technology improves density. HBM4, expected 2025-2026, increases per-stack capacity but the demand growth curve remains steeper than supply expansion.

This three-vendor chokepoint means that a production disruption at any single vendor reduces global HBM supply by 20-60% with no short-term alternative. Unlike logic chips where TSMC has theoretical competitors (Intel Foundry, Samsung Foundry), HBM production requires specialized stacking expertise that cannot be quickly replicated.

## Challenges

HBM4 significantly increases per-stack capacity, which could ease the constraint if stacking efficiency improvements outpace demand growth. CXL-attached memory (Compute Express Link) offers an alternative memory architecture for some inference workloads that reduces HBM dependency. Samsung and Micron are both expanding capacity aggressively. The constraint is most acute in 2024-2026; by 2027-2028 the supply-demand balance may improve — but this depends on whether frontier training compute demand continues doubling every 9-10 months.

---

Relevant Notes:
- [[CoWoS advanced packaging is the binding bottleneck on AI compute scaling because TSMC near-monopoly on interposer technology gates total accelerator output regardless of chip design capability]] — HBM and CoWoS are independent but reinforcing bottlenecks
- [[value in industry transitions accrues to bottleneck positions in the emerging architecture not to pioneers or to the largest incumbents]] — SK Hynix holds the strongest bottleneck position in memory
- [[compute supply chain concentration is simultaneously the strongest AI governance lever and the largest systemic fragility because the same chokepoints that enable oversight create single points of failure]] — HBM is one of three chokepoints in the concentration/fragility paradox

Topics:
- [[manufacturing systems]]
