diff --git a/domains/manufacturing/CoWoS advanced packaging is the binding bottleneck on AI compute scaling because TSMC near-monopoly on interposer technology gates total accelerator output regardless of chip design capability.md b/domains/manufacturing/CoWoS advanced packaging is the binding bottleneck on AI compute scaling because TSMC near-monopoly on interposer technology gates total accelerator output regardless of chip design capability.md
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+---
+type: claim
+domain: manufacturing
+description: "TSMC CEO confirmed CoWoS sold out through 2026, Google cut TPU production targets — the bottleneck is not chip design but physical packaging capacity, and each new AI chip generation requires larger interposers worsening the constraint per generation"
+confidence: likely
+source: "Astra, Theseus compute infrastructure research 2026-03-24; TSMC CEO public statements, Google TPU production cuts"
+created: 2026-03-24
+secondary_domains: ["ai-alignment"]
+depends_on:
+  - "value in industry transitions accrues to bottleneck positions in the emerging architecture not to pioneers or to the largest incumbents"
+challenged_by:
+  - "Intel EMIB and other alternatives may break the TSMC CoWoS monopoly by 2027-2028"
+  - "chiplet architectures with smaller interposers could reduce packaging constraints"
+---
+
+# CoWoS advanced packaging is the binding bottleneck on AI compute scaling because TSMC near-monopoly on interposer technology gates total accelerator output regardless of chip design capability
+
+The AI compute supply chain's binding constraint is not chip design — it's packaging. TSMC's Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology is required to integrate AI accelerators with HBM memory into functional modules. TSMC holds near-monopoly on this capability, and capacity is sold out through 2026.
+
+TSMC's CEO publicly confirmed the packaging bottleneck. Google has already cut TPU production targets due to CoWoS constraints. NVIDIA commands over 60% of CoWoS allocation, meaning its competitors fight over the remaining ~40% regardless of how good their chip designs are.
+
+The constraint worsens per generation: each new AI chip generation requires larger silicon interposers to accommodate more HBM stacks and wider memory bandwidth. NVIDIA's Blackwell GB200 NVL72 is a full-rack solution requiring massive packaging complexity. The trend toward system-level integration (entire racks as the unit of compute) amplifies packaging demand faster than capacity can expand.
+
+This makes CoWoS allocation the most consequential bottleneck position in the AI compute supply chain. Whoever controls packaging allocation controls who can ship AI hardware. This is a textbook case of [[value in industry transitions accrues to bottleneck positions in the emerging architecture not to pioneers or to the largest incumbents]] — TSMC's packaging division holds more leverage over AI scaling than any chip designer.
+
+## Challenges
+
+Intel's EMIB (Embedded Multi-die Interconnect Bridge) technology is gaining interest as a CoWoS alternative and could reach comparable capability by 2027-2028. Chiplet architectures with smaller interposers could reduce per-chip packaging demand. TSMC is aggressively expanding CoWoS capacity. The bottleneck is real in 2024-2026 but may ease by 2027-2028 as alternatives mature and capacity expands. The question is whether AI compute demand growth outpaces packaging supply expansion — current projections suggest demand wins through at least 2027.
+
+---
+
+Relevant Notes:
+- [[value in industry transitions accrues to bottleneck positions in the emerging architecture not to pioneers or to the largest incumbents]] — CoWoS allocation is THE bottleneck position in AI compute
+- [[compute supply chain concentration is simultaneously the strongest AI governance lever and the largest systemic fragility because the same chokepoints that enable oversight create single points of failure]] — packaging concentration is a key component of the governance/fragility paradox
+- [[physical infrastructure constraints on AI scaling create a natural governance window because packaging memory and power bottlenecks operate on 2-10 year timescales while capability research advances in months]] — packaging is the 2-3 year timescale constraint
+- [[the atoms-to-bits spectrum positions industries between defensible-but-linear and scalable-but-commoditizable with the sweet spot where physical data generation feeds software that scales independently]] — NVIDIA's packaging allocation is an atoms-layer moat feeding bits-layer dominance
+
+Topics:
+- [[manufacturing systems]]