domains/energy/AI datacenter power demand creates a 5-10 year infrastructure lag because grid construction and interconnection cannot match the pace of chip design cycles.md

@@ -1,42 +0,0 @@
----
-type: claim
-domain: energy
-description: "Projected 8-9% of US electricity by 2030 for datacenters, nuclear deals cover 2-3 GW near-term against 25-30 GW needed, grid interconnection averages 5+ years with only 20% of projects reaching commercial operation"
-confidence: likely
-source: "Astra, Theseus compute infrastructure research 2026-03-24; IEA, Goldman Sachs April 2024, de Vries 2023 in Joule, grid interconnection queue data"
-created: 2026-03-24
-secondary_domains: ["ai-alignment", "manufacturing"]
-depends_on:
-  - "power is the binding constraint on all space operations because every capability from ISRU to manufacturing to life support is power-limited"
-  - "knowledge embodiment lag means technology is available decades before organizations learn to use it optimally creating a productivity paradox"
-challenged_by:
-  - "Nuclear SMRs and modular gas turbines may provide faster power deployment than traditional grid construction"
-  - "Efficiency improvements in inference hardware may reduce power demand growth below current projections"
----
-
-# AI datacenter power demand creates a 5-10 year infrastructure lag because grid construction and interconnection cannot match the pace of chip design cycles
-
-AI datacenter power demand is projected to consume 8-9% of US electricity by 2030, up from ~2.5% in 2024. This represents 25-30 GW of additional capacity needed. But new power generation takes 3-7 years to build, and US grid interconnection queues average 5+ years with only ~20% of projects reaching commercial operation.
-
-The timescale mismatch is severe: chip design cycles operate on 1-2 year cadences (NVIDIA releases a new architecture annually), algorithmic efficiency improvements happen in months, but the power infrastructure to run the chips takes 5-10 years. This is the longest-horizon constraint on AI compute scaling and the one least susceptible to engineering innovation.
-
-Nuclear power deals for AI datacenters have been announced: Microsoft-Constellation (Three Mile Island restart), Amazon-X-Energy (SMRs), Google-Kairos (advanced fission). These cover 2-3 GW near-term — meaningful but an order of magnitude short of the projected 25-30 GW need. The rest must come from gas, renewables+storage, or grid expansion that faces permitting, construction, and interconnection delays.
-
-This creates a structural parallel with space development: [[power is the binding constraint on all space operations because every capability from ISRU to manufacturing to life support is power-limited]]. The same pattern applies terrestrially — every AI capability is ultimately power-limited, and the power infrastructure cannot match the pace of capability demand.
-
-The energy permitting timeline now exceeds construction timelines in many jurisdictions — a governance gap directly analogous to the technology-governance lag in space, where regulatory frameworks haven't adapted to the pace of technological change.
-
-## Challenges
-
-Nuclear SMRs (NuScale, X-Energy, Kairos) and modular gas turbines may provide faster power deployment than traditional grid construction, potentially compressing the lag from 5-10 years to 3-5 years. Efficiency improvements in inference hardware (the training-to-inference shift favoring power-efficient architectures) may reduce demand growth below current projections. Some hyperscalers are building private power infrastructure, bypassing the grid interconnection queue entirely. But even optimistic scenarios show power demand growing faster than supply through at least 2028-2030.
-
----
-
-Relevant Notes:
-- [[power is the binding constraint on all space operations because every capability from ISRU to manufacturing to life support is power-limited]] — the same power constraint applies terrestrially for AI
-- [[physical infrastructure constraints on AI scaling create a natural governance window because packaging memory and power bottlenecks operate on 2-10 year timescales while capability research advances in months]] — power is the longest-horizon constraint in Theseus's governance window
-- [[knowledge embodiment lag means technology is available decades before organizations learn to use it optimally creating a productivity paradox]] — grid modernization follows the same lag pattern as electrification
-- [[fusion contributing meaningfully to global electricity is a 2040s event at the earliest because 2026-2030 demonstrations must succeed before capital flows to pilot plants that take another decade to build]] — fusion cannot solve the AI power problem in the relevant timeframe
-
-Topics:
-- [[energy systems]]

domains/manufacturing/CoWoS advanced packaging is the binding bottleneck on AI compute scaling because TSMC near-monopoly on interposer technology gates total accelerator output regardless of chip design capability.md

@@ -1,39 +0,0 @@
----
-type: claim
-domain: manufacturing
-description: "TSMC CEO confirmed CoWoS sold out through 2026, Google cut TPU production targets — the bottleneck is not chip design but physical packaging capacity, and each new AI chip generation requires larger interposers worsening the constraint per generation"
-confidence: likely
-source: "Astra, Theseus compute infrastructure research 2026-03-24; TSMC CEO public statements, Google TPU production cuts"
-created: 2026-03-24
-secondary_domains: ["ai-alignment"]
-depends_on:
-  - "value in industry transitions accrues to bottleneck positions in the emerging architecture not to pioneers or to the largest incumbents"
-challenged_by:
-  - "Intel EMIB and other alternatives may break the TSMC CoWoS monopoly by 2027-2028"
-  - "chiplet architectures with smaller interposers could reduce packaging constraints"
----
-
-# CoWoS advanced packaging is the binding bottleneck on AI compute scaling because TSMC near-monopoly on interposer technology gates total accelerator output regardless of chip design capability
-
-The AI compute supply chain's binding constraint is not chip design — it's packaging. TSMC's Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology is required to integrate AI accelerators with HBM memory into functional modules. TSMC holds near-monopoly on this capability, and capacity is sold out through 2026.
-
-TSMC's CEO publicly confirmed the packaging bottleneck. Google has already cut TPU production targets due to CoWoS constraints. NVIDIA commands over 60% of CoWoS allocation, meaning its competitors fight over the remaining ~40% regardless of how good their chip designs are.
-
-The constraint worsens per generation: each new AI chip generation requires larger silicon interposers to accommodate more HBM stacks and wider memory bandwidth. NVIDIA's Blackwell GB200 NVL72 is a full-rack solution requiring massive packaging complexity. The trend toward system-level integration (entire racks as the unit of compute) amplifies packaging demand faster than capacity can expand.
-
-This makes CoWoS allocation the most consequential bottleneck position in the AI compute supply chain. Whoever controls packaging allocation controls who can ship AI hardware. This is a textbook case of [[value in industry transitions accrues to bottleneck positions in the emerging architecture not to pioneers or to the largest incumbents]] — TSMC's packaging division holds more leverage over AI scaling than any chip designer.
-
-## Challenges
-
-Intel's EMIB (Embedded Multi-die Interconnect Bridge) technology is gaining interest as a CoWoS alternative and could reach comparable capability by 2027-2028. Chiplet architectures with smaller interposers could reduce per-chip packaging demand. TSMC is aggressively expanding CoWoS capacity. The bottleneck is real in 2024-2026 but may ease by 2027-2028 as alternatives mature and capacity expands. The question is whether AI compute demand growth outpaces packaging supply expansion — current projections suggest demand wins through at least 2027.
-
----
-
-Relevant Notes:
-- [[value in industry transitions accrues to bottleneck positions in the emerging architecture not to pioneers or to the largest incumbents]] — CoWoS allocation is THE bottleneck position in AI compute
-- [[compute supply chain concentration is simultaneously the strongest AI governance lever and the largest systemic fragility because the same chokepoints that enable oversight create single points of failure]] — packaging concentration is a key component of the governance/fragility paradox
-- [[physical infrastructure constraints on AI scaling create a natural governance window because packaging memory and power bottlenecks operate on 2-10 year timescales while capability research advances in months]] — packaging is the 2-3 year timescale constraint
-- [[the atoms-to-bits spectrum positions industries between defensible-but-linear and scalable-but-commoditizable with the sweet spot where physical data generation feeds software that scales independently]] — NVIDIA's packaging allocation is an atoms-layer moat feeding bits-layer dominance
-
-Topics:
-- [[manufacturing systems]]

domains/manufacturing/HBM memory supply concentration creates a three-vendor chokepoint where all production is sold out through 2026 gating every AI training system regardless of processor architecture.md

@@ -1,38 +0,0 @@
----
-type: claim
-domain: manufacturing
-description: "SK Hynix, Samsung, and Micron produce all HBM globally with each GB requiring 3-4x the wafer capacity of DDR5 — structural supply tension worsens as AI chips demand more memory bandwidth per generation"
-confidence: likely
-source: "Astra, Theseus compute infrastructure research 2026-03-24; SK Hynix/Samsung/Micron CFO public confirmations"
-created: 2026-03-24
-secondary_domains: ["ai-alignment"]
-depends_on:
-  - "value in industry transitions accrues to bottleneck positions in the emerging architecture not to pioneers or to the largest incumbents"
-challenged_by:
-  - "HBM4 increases per-stack capacity which could ease the constraint if stacking efficiency improves faster than demand grows"
-  - "alternative memory architectures like CXL-attached memory may reduce HBM dependency for some workloads"
----
-
-# HBM memory supply concentration creates a three-vendor chokepoint where all production is sold out through 2026 gating every AI training system regardless of processor architecture
-
-High Bandwidth Memory (HBM) is required for every modern AI accelerator — NVIDIA H100/H200/B200, AMD MI300X, Google TPU v5. Three companies produce all of it globally: SK Hynix (~50% market share), Samsung (~40%), and Micron (~10%). All three have confirmed their HBM supply is sold out through 2026.
-
-The structural tension is physical: each GB of HBM requires 3-4x the silicon wafer capacity of standard DDR5 because HBM stacks multiple DRAM dies vertically using through-silicon vias (TSVs) and micro-bumps. This means HBM production directly competes with commodity DRAM production for wafer capacity, creating a zero-sum allocation problem for memory fabs.
-
-Each new AI chip generation demands more HBM per accelerator: NVIDIA's B200 uses HBM3e stacks with higher bandwidth than H100's HBM3. The trend toward larger models and longer context windows increases memory requirements faster than stacking technology improves density. HBM4, expected 2025-2026, increases per-stack capacity but the demand growth curve remains steeper than supply expansion.
-
-This three-vendor chokepoint means that a production disruption at any single vendor reduces global HBM supply by 20-60% with no short-term alternative. Unlike logic chips where TSMC has theoretical competitors (Intel Foundry, Samsung Foundry), HBM production requires specialized stacking expertise that cannot be quickly replicated.
-
-## Challenges
-
-HBM4 significantly increases per-stack capacity, which could ease the constraint if stacking efficiency improvements outpace demand growth. CXL-attached memory (Compute Express Link) offers an alternative memory architecture for some inference workloads that reduces HBM dependency. Samsung and Micron are both expanding capacity aggressively. The constraint is most acute in 2024-2026; by 2027-2028 the supply-demand balance may improve — but this depends on whether frontier training compute demand continues doubling every 9-10 months.
-
----
-
-Relevant Notes:
-- [[CoWoS advanced packaging is the binding bottleneck on AI compute scaling because TSMC near-monopoly on interposer technology gates total accelerator output regardless of chip design capability]] — HBM and CoWoS are independent but reinforcing bottlenecks
-- [[value in industry transitions accrues to bottleneck positions in the emerging architecture not to pioneers or to the largest incumbents]] — SK Hynix holds the strongest bottleneck position in memory
-- [[compute supply chain concentration is simultaneously the strongest AI governance lever and the largest systemic fragility because the same chokepoints that enable oversight create single points of failure]] — HBM is one of three chokepoints in the concentration/fragility paradox
-
-Topics:
-- [[manufacturing systems]]

domains/manufacturing/TSMC manufactures 92 percent of advanced logic chips making Taiwan the single largest physical vulnerability in global technology infrastructure.md

@@ -1,38 +0,0 @@
----
-type: claim
-domain: manufacturing
-description: "Geographic diversification underway (Arizona 92% yield, Samsung, Intel Foundry) but most advanced processes remain Taiwan-first through 2027-2028 — a disruption would immediately halt AI accelerator and smartphone chip production globally"
-confidence: likely
-source: "Astra, Theseus compute infrastructure research 2026-03-24; Chris Miller 'Chip War', CSET Georgetown, TSMC market share data"
-created: 2026-03-24
-secondary_domains: ["ai-alignment"]
-depends_on:
-  - "optimization for efficiency without regard for resilience creates systemic fragility because interconnected systems transmit and amplify local failures into cascading breakdowns"
-challenged_by:
-  - "TSMC Arizona achieving 92% yield shows geographic diversification is technically feasible and progressing"
-  - "Intel Foundry and Samsung Foundry provide theoretical alternatives for some advanced processes"
----
-
-# TSMC manufactures 92 percent of advanced logic chips making Taiwan the single largest physical vulnerability in global technology infrastructure
-
-TSMC fabricates approximately 92% of the world's most advanced logic chips (7nm and below). This includes virtually all AI accelerators (NVIDIA, AMD, Google TPUs), all Apple processors, and most leading-edge smartphone chips. No other concentration of critical manufacturing capability exists in any industry — not energy, not aerospace, not pharmaceuticals.
-
-Taiwan's geographic position creates compounding risk: military tension with China (Taiwan Strait), seismic vulnerability (Taiwan sits on the Pacific Ring of Fire), and energy dependence (Taiwan imports 98% of its energy). A military conflict, blockade, major earthquake, or prolonged power disruption would immediately halt production of the chips that run AI systems, smartphones, datacenters, and military systems globally.
-
-Geographic diversification is real but early. TSMC's Arizona fab has achieved 92% yield — approaching Taiwan levels — which demonstrates that knowledge transfer is feasible. But the most advanced processes (N2, N3P) remain Taiwan-first through at least 2027-2028. The Arizona fabs produce at mature nodes; the leading edge is still concentrated in Hsinchu.
-
-Intel Foundry and Samsung Foundry provide theoretical alternatives, but neither has demonstrated the yields, capacity, or customer trust to absorb TSMC's share. Intel's roadmap (18A, 14A) is promising but unproven at scale. Samsung's foundry business has persistently underperformed TSMC on yield. The competitive gap is narrowing but remains substantial.
-
-## Challenges
-
-TSMC Arizona's 92% yield achievement is the strongest counterargument — it proves that geographic diversification is technically achievable, not just aspirational. If CHIPS Act subsidies continue and yield parity is maintained, the US could have meaningful advanced chip production by 2028-2030. Japan (TSMC Kumamoto) and Germany (TSMC Dresden) provide additional diversification. The concentration is a snapshot in time, not a permanent condition — but the transition period (2024-2028) is the window of maximum vulnerability.
-
----
-
-Relevant Notes:
-- [[optimization for efficiency without regard for resilience creates systemic fragility because interconnected systems transmit and amplify local failures into cascading breakdowns]] — the semiconductor supply chain is a textbook case of efficiency-optimized fragility
-- [[compute supply chain concentration is simultaneously the strongest AI governance lever and the largest systemic fragility because the same chokepoints that enable oversight create single points of failure]] — Taiwan concentration is the largest single component of compute supply fragility
-- [[semiconductor fab cost escalation means each new process node is a nation-state commitment because 20B-plus capital costs and multi-year construction create irreversible geographic path dependence]] — the economics that drove Taiwan concentration
-
-Topics:
-- [[manufacturing systems]]

domains/manufacturing/semiconductor fab cost escalation means each new process node is a nation-state commitment because 20B-plus capital costs and multi-year construction create irreversible geographic path dependence.md

@@ -1,39 +0,0 @@
----
-type: claim
-domain: manufacturing
-description: "TSMC Arizona fab cost $40B+, Samsung Taylor $17B, Intel Ohio $20B — fab economics drive geographic concentration because only nation-state-level subsidies (CHIPS Act $52.7B) can justify the investment"
-confidence: likely
-source: "Astra, Theseus compute infrastructure research 2026-03-24; CHIPS Act public records, TSMC/Samsung/Intel fab announcements"
-created: 2026-03-24
-secondary_domains: ["ai-alignment"]
-depends_on:
-  - "the personbyte is a fundamental quantization limit on knowledge accumulation forcing all complex production into networked teams"
-  - "knowledge embodiment lag means technology is available decades before organizations learn to use it optimally creating a productivity paradox"
-challenged_by:
-  - "CHIPS Act and EU Chips Act subsidies may successfully diversify fab geography if sustained over multiple fab generations"
-  - "advanced packaging may become more geographically distributed than logic fabrication reducing the single-geography risk"
----
-
-# Semiconductor fab cost escalation means each new process node is a nation-state commitment because 20B-plus capital costs and multi-year construction create irreversible geographic path dependence
-
-Leading-edge semiconductor fabs now cost $20B+ to build and take 3-5 years to construct. TSMC's Arizona complex is projected at $40B+ for two fabs. Samsung's Taylor, Texas fab costs $17B. Intel's Ohio fabs are projected at $20B. These are not business investments — they are nation-state-level commitments that only proceed with massive public subsidies (US CHIPS Act $52.7B, EU Chips Act €43B, Japan ¥3.9T).
-
-The cost escalation is structural: each new process node requires more complex lithography (EUV at $150M+ per tool, with only ASML as supplier), more processing steps, more precise materials, and more specialized workforce. The cost per transistor has stopped declining at the leading edge even as density continues improving — the economic scaling that drove Moore's Law is over, replaced by performance-per-watt scaling that costs more per fab generation.
-
-This creates irreversible geographic path dependence: once a nation commits $20-40B to a fab, the workforce training, supplier ecosystem, and infrastructure investment lock in that geography for decades. TSMC choosing Arizona, Samsung choosing Taylor, Intel choosing Ohio — these are 30-year bets that shape where advanced chips can be made for a generation.
-
-The personbyte constraint is directly relevant: a modern fab requires thousands of specialized workers operating in a knowledge network that takes years to develop. TSMC's Arizona fab initially struggled with yield because the knowledge network hadn't transferred — the tools were identical but the tacit knowledge wasn't. The 92% yield now achieved represents successful knowledge embodiment, not just equipment installation.
-
-## Challenges
-
-CHIPS Act subsidies are successfully pulling fab investment to the US — the question is whether this is a one-time relocation or a sustained diversification. If subsidies are not renewed for subsequent fab generations, investment may revert to existing clusters (Taiwan, South Korea) where the knowledge networks and supplier ecosystems are deepest. Advanced packaging may be more geographically distributable than logic fabrication, which could partially reduce single-geography risk even if fab concentration persists.
-
----
-
-Relevant Notes:
-- [[the personbyte is a fundamental quantization limit on knowledge accumulation forcing all complex production into networked teams]] — fab operation requires deep knowledge networks that constrain geographic diversification
-- [[knowledge embodiment lag means technology is available decades before organizations learn to use it optimally creating a productivity paradox]] — TSMC Arizona yield gap illustrates knowledge embodiment in manufacturing
-- [[compute supply chain concentration is simultaneously the strongest AI governance lever and the largest systemic fragility because the same chokepoints that enable oversight create single points of failure]] — fab cost escalation drives the concentration this claim describes
-
-Topics:
-- [[manufacturing systems]]