teleo-codex/domains/space-development/modern AI accelerators are more radiation-tolerant than expected because Google TPU testing showed no hard failures up to 15 krad suggesting consumer chips may survive LEO environments.md
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astra: batch 6 — 10 orbital compute & space data center claims
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- Distributed LEO inference networks (4-20ms latency)
- AI accelerator radiation tolerance (Google TPU 15 krad test)
- On-orbit satellite data processing (proven near-term use case)
- Orbital AI training incompatibility (bandwidth gap)
- Orbital compute servicing impossibility (trilemma)
- Orbital data centers overview (speculative but serious players)
- Five enabling technologies requirement (none at readiness)
- Solar irradiance advantage (8-10x ground-based)
- Thermal physics blocker (space is thermos not freezer)
- Starcloud company analysis (first GPU in orbit, SpaceX dependency)

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
2026-03-27 13:13:59 +00:00

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type domain description confidence source created depends_on
claim space-development Google tested Trillium v6e TPUs in a 67 MeV proton beam with no hard failures up to 15 krad total ionizing dose — challenging the assumption that AI compute requires expensive radiation-hardened hardware experimental Astra, Google Project Suncatcher feasibility study late 2025 2026-02-17
space-based computing at datacenter scale is blocked by thermal physics because radiative cooling in vacuum requires surface areas that grow faster than compute density

Modern AI accelerators are more radiation-tolerant than expected because Google TPU testing showed no hard failures up to 15 krad suggesting consumer chips may survive LEO environments

Google's Project Suncatcher feasibility study included proton beam testing of their Trillium (v6e) TPU accelerators at 67 MeV. The result was surprising: no hard failures up to 15 krad(Si) total ionizing dose. This is a genuinely important data point because the conventional assumption in space systems engineering is that commercial-grade semiconductors require expensive radiation hardening (or radiation-hardened by design alternatives that are generations behind in performance) to survive in orbit.

Space radiation damages electronics through three mechanisms. Single Event Upsets (SEUs) are bit flips from high-energy particle strikes -- correctable with error-correcting code memory but they increase compute overhead. Total Ionizing Dose (TID) is cumulative degradation that shifts threshold voltages and increases leakage current over the satellite's operational lifetime. Single Event Latchup can cause destructive overcurrent conditions requiring power cycling or permanently damaging circuits.

The Google result addresses TID specifically and suggests that modern process nodes (5nm and below) may be inherently more radiation-tolerant than older process generations. If confirmed across other chip architectures, this significantly de-risks the hardware side of orbital compute. It does not eliminate the SEU problem -- bit flips will still occur at elevated rates compared to terrestrial operation -- but ECC memory and algorithmic redundancy can manage this for inference workloads where occasional soft errors are tolerable.

Critical caveats: Starcloud operating an H100 in orbit for a demonstration is fundamentally different from operating thousands of H100s reliably for years. Long-duration LEO operation accumulates dose over years, and the South Atlantic Anomaly creates radiation hotspots that elevate local dose rates. Still, the Google result shifts the prior: radiation hardening may be less of a showstopper than thermal management for orbital compute viability.

Evidence

  • Google Trillium v6e TPU proton beam testing — no hard failures to 15 krad(Si)
  • Modern 5nm process node characteristics suggesting inherent radiation tolerance
  • Starcloud H100 orbital demonstration (single GPU, short duration)

Challenges

Long-duration operation over years with cumulative dose, SAA transits, and solar particle events remains uncharacterized for commercial AI hardware. The TPU result may not generalize to GPU architectures.


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